A low overhead fault tolerant FPGA with new connection box

Abstract

With the increasing process variations in advanced semiconductor technologies, fault tolerance has become one of several essential issues in building Field Programmable Gate Arrays (FPGAs). Unfortunately, there has been much less fault tolerance work previously done on FPGA interconnects, which take up to 90% of an FPGA device, than on its logic blocks. In view of this, we develop a low overhead connection block architecture, which improves the fault tolerance of FPGA interconnects. By testing 10 MCNC benchmarks on the new architecture, FPGA fault tolerance reaches levels comparable to adding 2 extra wire tracks per channel, with the average timing overhead below 2.5% and the area overheads of only 2.5% - 4%.