Low-power device design of fully-depleted SOI MOSFETs

Abstract

A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.