A bit-serial arithmetic unit for rational arithmetic

Peter Kornerup, D. Matula
{"title":"A bit-serial arithmetic unit for rational arithmetic","authors":"Peter Kornerup, D. Matula","doi":"10.1109/ARITH.1987.6158705","DOIUrl":null,"url":null,"abstract":"We describe a binary implementation of an algorithm of Gosper to compute the sum, difference, product, quotient and certain rational functions of two rational operands applicable to integrated approximate and exact rational computation. The arithmetic unit we propose is an eight register computation cell with bit serial input and output employing the binary lexicographic continued fraction (LCF) representation of the rational operands. The operands and results are processed in a most-significant-bit first on-line fashion with bit level logic leading to less delay in the computation cell when compared to operation on the full partial quotients of the standard continued fraction representation. Minimization of delay is investigated with the aim of supporting greater throughput in cascaded parallel computation with such computation cells.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1987.6158705","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We describe a binary implementation of an algorithm of Gosper to compute the sum, difference, product, quotient and certain rational functions of two rational operands applicable to integrated approximate and exact rational computation. The arithmetic unit we propose is an eight register computation cell with bit serial input and output employing the binary lexicographic continued fraction (LCF) representation of the rational operands. The operands and results are processed in a most-significant-bit first on-line fashion with bit level logic leading to less delay in the computation cell when compared to operation on the full partial quotients of the standard continued fraction representation. Minimization of delay is investigated with the aim of supporting greater throughput in cascaded parallel computation with such computation cells.
有理数算术的位串行算术单元
描述了一种计算两个有理数的和、差、积、商和某些有理数函数的算法的二进制实现,适用于积分近似和精确有理数计算。我们提出的算术单元是一个8寄存器的计算单元,具有位串行输入和输出,采用二进制字典连续分数(LCF)表示有理数。操作数和结果以最有效位优先在线方式处理,与对标准连分数表示的全部分商的操作相比,位级逻辑导致计算单元中的延迟更小。研究了延迟最小化的问题,目的是在级联并行计算中支持更大的吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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