Parasitic charge movement in floating-gate array programming

Abstract

Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.