Analysis of coupling-induced jitter in FPGA transceiver

Abstract

This paper analyses jitter increase mechanism due to parallel IO simultaneous switching noise (SSN), while FPGA transceiver operates at multi-gigabit data rates or higher. Several jitter measurement methods and relevant simulations are used to diagnose noise sources and coupling paths. This paper illustrates that transmitter jitter profile is related to power supply noise and inductive crosstalk characteristics. These findings helped improve PDN design resulting in better device jitter performance.