FPGA Implementation of Low-Latency Robust Asynchronous Interfaces for GALS Systems

Abstract

Complex digital systems must necessarily be based on the "System-on-Chip – SoC" concept. A natural implementation of SoC circuit uses global clock, but in DSM technology (Deep-Sub-Micron) global clock signal causes several problems. An interesting style for SoC design that reduces the problems of the global clock is the GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system, shows to be the asynchronous interface. This paper proposes a novel asynchronous wrapper based on a unique port controller aiming to the point-to-point GALS style and easily generalized to multi-point GALS systems. The proposed asynchronous wrapper allows the communication between modules to be performed in the two-phase handshake protocol, which reduces the latency time when compared to the previous ones, and it is robust with respect to essential hazard. A comparison with seven wrappers found in literature shows that the proposed wrapper leads to an average reduction in latency time of 61.1% and average reduction in area of 58% in the FPGA (Field Programmable Gated array) platform.