A scalable architecture for low-latency market-data processing on FPGA

Abstract

The speed of market data processing is a key factor to grab the gains and losses of instant trading profits. Typically, the market data processing systems are deployed on software platforms, which introduce high and unpredictable processing latencies. In this paper, we propose a scalable architecture for low-latency market-data processing on Field Programmable Gate Array (FPGA). A market-data processing IP library is implemented by the high-level synthesis (HLS) which automatically translates the C-coded market-data decoders to logic-coded ones. Based on the IP library, we propose a bus-based architecture of market-data decoding engine. A constructor is proposed to automatically build the decoding engines for different market-data templates. We demonstrate our design within a Xilinx Kintex-7 FPGA using three Chinese A-share templates and multiple history market-data sets. Our implementation achieves an ultra-low latency of market data processing, 0.5~1.3us per message on average, 1~2 orders of magnitude faster than a comparable software implementation.