A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator

Abstract

A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).