Jan Richter-Brockmann, Pascal Sasdrich, Florian Bache, T. Güneysu
{"title":"Concurrent error detection revisited: hardware protection against fault and side-channel attacks","authors":"Jan Richter-Brockmann, Pascal Sasdrich, Florian Bache, T. Güneysu","doi":"10.1145/3407023.3407046","DOIUrl":null,"url":null,"abstract":"Fault Injection Analysis (FIA) and Side-Channel Analysis (SCA) are considered among the most serious threats to cryptographic implementations and require dedicated countermeasures to ensure protection through the entire life-cycle of the implementations. In this work, our contribution is twofold. First, we present a novel orthogonal layout of linear Error-Correcting Codes (ECCs) to adjust classical Concurrent Error Detection (CED) to an adversary model that assumes precisely induced single-bit faults which, with a certain non-negligible probability, will affect adjacent bits. Second, we combine our orthogonal error correction technique with a state-of-the-art SCA protection mechanism to demonstrate resistance against both threats. Eventually, using AES as a case study, our approach can correct entirely faulted bytes while it does not exhibit detectable first-order side-channel leakage using 200 million power traces and Test Vector Leakage Assessment (TVLA) as state-of-the-art leakage assessment methodology. Furthermore, our hardware implementations reduce the area and resource consumption by 14.9% -- 18.3% for recent technology nodes (compared to a conventional CED scheme).","PeriodicalId":121225,"journal":{"name":"Proceedings of the 15th International Conference on Availability, Reliability and Security","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 15th International Conference on Availability, Reliability and Security","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3407023.3407046","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Fault Injection Analysis (FIA) and Side-Channel Analysis (SCA) are considered among the most serious threats to cryptographic implementations and require dedicated countermeasures to ensure protection through the entire life-cycle of the implementations. In this work, our contribution is twofold. First, we present a novel orthogonal layout of linear Error-Correcting Codes (ECCs) to adjust classical Concurrent Error Detection (CED) to an adversary model that assumes precisely induced single-bit faults which, with a certain non-negligible probability, will affect adjacent bits. Second, we combine our orthogonal error correction technique with a state-of-the-art SCA protection mechanism to demonstrate resistance against both threats. Eventually, using AES as a case study, our approach can correct entirely faulted bytes while it does not exhibit detectable first-order side-channel leakage using 200 million power traces and Test Vector Leakage Assessment (TVLA) as state-of-the-art leakage assessment methodology. Furthermore, our hardware implementations reduce the area and resource consumption by 14.9% -- 18.3% for recent technology nodes (compared to a conventional CED scheme).