Design and implementation of telescopic OTA in 8 bit second-order continuous-time band-pass Sigma-Delta ADC

G. Jamuna, S. Yellampalli, S. Swetha
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引用次数: 5

Abstract

In this paper, a technique to design the 8 bit continuous-time band-pass Sigma-Delta converters for 70 MHz is presented. The conversion from discrete-time (z-domain) loop-filter transfer function into continuous-time (s-domain) is done by using Impulse-invariant-transformation. The transconductor-capacitor filter is used to implement continuous-time loop-filter. A latched-type comparator and a TSPC D Flip-flop are being used as the quantizer of the Sigma-Delta converter. The decimation filter is designed by a CIC Filter and an FIR filter for high-speed. A full adder cell and a TSPC D Flip-flop are used as basic building blocks of CIC Filter and FIR Filter. The 8 bit second-order continuous Sigma-Delta converter circuit has been implemented in Cadence using 180nm CMOS technology and the total power consumption is 34.48 mW. At a supply voltage of 3 V, the maximum SNR is measured to be 49.92 dB, ENOB is measured to be 8.29 bites, propagation delay is measured to be 2.56ns which corresponds to a resolution of 8 bits.
8位二阶连续带通Sigma-Delta ADC中伸缩OTA的设计与实现
本文介绍了一种用于70mhz的8位连续带通σ - δ转换器的设计方法。利用脉冲不变变换实现了离散时间(z域)环滤波传递函数到连续时间(s域)的转换。采用跨导体-电容滤波器实现连续时间环路滤波。锁存式比较器和TSPC D触发器被用作Sigma-Delta转换器的量化器。采用CIC滤波器和FIR滤波器设计了高速抽取滤波器。一个完整的加法器单元和一个TSPC D触发器被用作CIC滤波器和FIR滤波器的基本构建块。采用180nm CMOS技术的8位二阶连续Sigma-Delta转换器电路已在Cadence上实现,总功耗为34.48 mW。在电源电压为3 V时,测得最大信噪比为49.92 dB, ENOB为8.29 bits,传输延迟为2.56ns,对应于8位的分辨率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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