{"title":"Extensible and reconfigurable multi-core processor connecting method","authors":"Wenli Tu, Hong Guo, Shuang Chen, Jin Zhang","doi":"10.1109/ICIEA.2018.8398140","DOIUrl":null,"url":null,"abstract":"With the development of the integrated circuit manufacturing process, it is difficult to further improve the performance of single-core processor. More and more attention has been paid to multi-core processor. The paper discloses an extensible re-configurable multi-core processor connection method. The method constructs an on-chip network through an on-chip router and a on-chip connection for connecting programmable logic blocks. This paper constructs an extensible re-configurable multi-core processor connection method based on the on-chip network. A plurality of configured processing units can communicate through the on-chip network. This method implements the on-chip network connection of programmable logic blocks. It can reduce the wiring area, improve the efficiency of the use of on-chip area and make the chip structure easier to expand.","PeriodicalId":140420,"journal":{"name":"2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2018.8398140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
With the development of the integrated circuit manufacturing process, it is difficult to further improve the performance of single-core processor. More and more attention has been paid to multi-core processor. The paper discloses an extensible re-configurable multi-core processor connection method. The method constructs an on-chip network through an on-chip router and a on-chip connection for connecting programmable logic blocks. This paper constructs an extensible re-configurable multi-core processor connection method based on the on-chip network. A plurality of configured processing units can communicate through the on-chip network. This method implements the on-chip network connection of programmable logic blocks. It can reduce the wiring area, improve the efficiency of the use of on-chip area and make the chip structure easier to expand.