DVTG and Test Harnessing using Rosetta specifications

Abstract

Specification-based verification is increasingly being used when designing systems. In verification, the program under test is executed repeatedly and the obtained outputs and/or other parameters are compared against the expected values. This ensures that the implementation satisfies its specified functionality. We present a tool, DVTG [K. Ranganathan, (2001)], for automatically generating test vectors from Rosetta specifications. DVTG requires test requirements in XML format and test scenarios, to generate these test vectors. For a given set of input parameters, the vectors represent desired output parameter values for the program under test. They can be further translated to specific inputs to run more concrete simulations. Later on, we discuss another tool, Test Harness, to authenticate a test program. We verify the output generated during test harnessing against the acceptance criteria generated from the specifications. We have proposed two major verifications to be performed during test harnessing, verifying the expected behavior and real-time requirements for the test program.