Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao
{"title":"A 0.4mm3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip Antenna","authors":"Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao","doi":"10.1109/vlsitechnologyandcir46769.2022.9830235","DOIUrl":null,"url":null,"abstract":"We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830235","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.