A 32/spl times/32 self-timed multiplier with early completion

Abstract

We designed a 32/spl times/32 self-timed multiplier with DCVSL. The multiplier supports both signed and unsigned integer multiplication, and adopts an early completion scheme for fast operation. We proposed a new 4-phase handshake circuit that fits well with DCVSL. We implement the proposed multiplier with 0.6 /spl mu/m CMOS technology, and simulate the circuit with HSPICE. The latency of the multiplier is between 11.7 ns and 98.7 ns. The size of the core multiplier is about 1.8 mm/spl times/1.4 mm.