Estimation of maximum currents for fault tolerant design of power distribution systems in integrated circuits

[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers Pub Date : 1989-06-21 DOI:10.1109/FTCS.1989.105586

Shamsul Chowdhury

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Abstract

Current flow in power distribution systems inside an integrated circuit (IC), especially in VLSI and wafer-scale ICs, causes problems of voltage drop and metal migration, leading to logic malfunction, reduction in operating speed, and reduction in the expected life span of a chip. Accurate estimations of currents are needed to design the power distribution systems so that they will withstand the adverse effects of current surges. During fabrication or as a result of aging, the power distribution systems may break at some weak points. As a result, some parts of the systems may have to route excessive amounts of currents. A power distribution system should be designed so that, in the presence of a limited number of these breaks, the system will deliver currents to the macro cells without violating some prescribed limits on voltage drops and without causing metal migration. The author deals with estimating currents in the segments of power distribution systems under fault conditions and develops guidelines for designing the systems so that the voltage drop and metal migration constraints with respect to these current estimates will not be violated.<>

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集成电路配电系统容错设计中最大电流的估计

集成电路(IC)内部配电系统中的电流流动，特别是在VLSI和晶圆级IC中，会引起电压下降和金属迁移问题，导致逻辑故障，降低运行速度，降低芯片的预期寿命。在设计配电系统时，需要对电流进行准确的估计，以使配电系统能够承受电流浪涌的不利影响。在制造过程中或由于老化，配电系统可能在一些薄弱环节发生故障。因此，系统的某些部分可能不得不输出过多的电流。在设计配电系统时，应使在这些断路的数量有限的情况下，系统将电流输送到宏观电池，而不会违反某些规定的电压降限制，也不会引起金属迁移。作者处理在故障条件下配电系统部分的电流估计，并制定了设计系统的指导方针，以便与这些电流估计有关的电压降和金属迁移限制不会被违反。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers

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