On using ATPG vectors for BIST TPG

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824104

T. Asakawa, K. Iwasaki

引用次数: 3

Abstract

We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method.

查看原文本刊更多论文

利用ATPG载体进行北京科技大学TPG的研究

本文提出了一种设计测试模式发生器(TPG)的方法，以在短时间内实现对故障卡滞的高故障覆盖率。TPG由移位寄存器和少量ROM组成，其中包含由ATPG工具生成的测试向量。实验结果表明，与基于lfsr的方法相比，我们的方法可以在较少的硬件开销下大幅减少实现高故障覆盖率所需的测试长度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

自引率

0.00%

发文量