Delay locked loop with linear delay element

Abstract

Delay locked loops (DLLs) and phase locked loops (PLLs) are used in synchronous digital systems in order to improve timings, i.e. to minimize negative effects of skew and jitter in the clock distribution network. In this paper, we propose an efficient DLL architecture implemented with linear delay element. Linearization is achieved by modifying the classical hardware structures of the bias and charge pump circuits (Y. Moon et al., 2000). Namely, in our proposal both circuits, instead of single ended use differential input/output structure. This allows us to realize process independent and temperature compensated DLL circuit. Simulation results, that relate to models of 1.2 /spl mu/m CMOS double-poly double-metal technology, show that the proposed DLL has linear delay regulation and stable lock-in for supply voltage, temperature, and parameter's technology process variations, in the full range of regulation.