Shang Hu, Rui Bai, Juncheng Wang, Xuefeng Chen, Jianxu Ma, Xin Wang, Yuanxi Zhang, Lei Wang, Y. Cai, Hao Yan, Jiangao Xuan, Yuan Li, M. Lu, Tao Xia, Liu Chang, Qi Nan, P. Chiang
{"title":"A 25Gb/s Optical CDR + Driver Transmitter Using 14Gb/s VCSELs in 40nm-CMOS","authors":"Shang Hu, Rui Bai, Juncheng Wang, Xuefeng Chen, Jianxu Ma, Xin Wang, Yuanxi Zhang, Lei Wang, Y. Cai, Hao Yan, Jiangao Xuan, Yuan Li, M. Lu, Tao Xia, Liu Chang, Qi Nan, P. Chiang","doi":"10.1109/CICTA.2018.8705945","DOIUrl":null,"url":null,"abstract":"A 25.78Gb/s optical transmitter with asymmetric equalizing driver and reference-less clock and data recovery (CDR) is presented in 40nm CMOS. A low power 3-tap asymmetric pulse-equalizer is proposed to extend bandwidth and compensate for the nonlinearity when using low-bandwidth 14Gb/s 850nm-VCSELs. A reference-less half-rate CDR with digital frequency-locked loop is integrated to recover the data and remove any input accumulated jitter. Measurement results demonstrate 25.78Gb/s optical link with error free operation (BER<10-12) over 100m fiber. Significant improvements are observed in the optical eye-opening, which increases the horizontal and vertical opening up to 25% and 15% respectively compared to the traditional pre-emphasis. The transmitter dissipates 280mW from 1.2V and 3.3V dual supplies, in which the VCSEL driver with equalizer consumes 128mW.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICTA.2018.8705945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A 25.78Gb/s optical transmitter with asymmetric equalizing driver and reference-less clock and data recovery (CDR) is presented in 40nm CMOS. A low power 3-tap asymmetric pulse-equalizer is proposed to extend bandwidth and compensate for the nonlinearity when using low-bandwidth 14Gb/s 850nm-VCSELs. A reference-less half-rate CDR with digital frequency-locked loop is integrated to recover the data and remove any input accumulated jitter. Measurement results demonstrate 25.78Gb/s optical link with error free operation (BER<10-12) over 100m fiber. Significant improvements are observed in the optical eye-opening, which increases the horizontal and vertical opening up to 25% and 15% respectively compared to the traditional pre-emphasis. The transmitter dissipates 280mW from 1.2V and 3.3V dual supplies, in which the VCSEL driver with equalizer consumes 128mW.