On Design of a Shared-Buffer based ATM Switch for Broadband ISDN

Abstract

This paper presents a shared buffer ATM switch architecture suitable for broadband integrated services digital networks. This switch mainly consists of 1K ATM-cell memory, a corresponding routing tag memory, two independent but cooperating memory control units along with associated multiplexers/demultiplexers and serial/parallel converters. The proposed shared-buffer switch architecture exploits the parallelization of memory operations required to perform efficient ATM switching with increased ATM cell processing time. A concept of switching efficiency at the hardware level namely, the switching-slot efliciency for a shared buffer ATM switch has been introduced. A design to enhance the switching slot efficiency of a shared buffer ATM switch by parallelizing memory operations within the switch has been proposed. Kevwords ATM switching, B-ISDN, performance evaluation, shared-buffer architecture, switching efficiency.