A Comparator with sub-mV offset in Deep Submicron Technology for Biomedical Applications

Abstract

This study presents a double-tail latched comparator with a sub-mV input offset voltage. The Input Offset Storage (IOS) and transistor sizing techniques were used to address the two leading contributors of offset, which are the preamplifier’s input pair, and the regenerative latch’s reset switches. The proposed circuit was implemented using 180 nm CMOS technology, and operated under a 1. 8V supply and 10 kHz clock frequency. Results show that the combination of techniques leads to a total input offset voltage of942 uV, which is equivalent to a 75% reduction with respect to the original configuration. Usage of the IOS technique results in a static power dissipation of 19.82 uW. This translates to an average power of 83.8 nW when measured over 100 cycles, which is the interval before the IOS phase is repeated. Overall, the design exhibits superior robustness against the effects of mismatches, making it suitable for precision applications, such as biomedical data converters.