Design a Low-Cost Majority Gate in QCA Nanotechnology

Abstract

CMOS-based devices have several limitations, such as hard lithography and high-energy consumption, which motivated researchers to looking for alternative methods. However, Quantum-dot Cellular Automata (QCA) is a new nanoscale method that provides a binary representation. The main building blocks in this technology are the inverter block and the 3-bit majority gate. The majority output is high when at least two of the inputs are high; otherwise, it is low. In contrast, the 5-bit majority gate is significant, where it is utilized for reducing the complexity in several circuits in QCA, such as adders and memories. Thus, designing the majority gate in an optimal form is important as it minimize the entire circuit complexity. In this paper, a new architecture of majority block (5-bit) has been suggested, which is executed in 3-layers with 17% improvement in terms of both circuit area and implementation cost. The QCADesigner tool is used in this work to build and simulate the proposed circuit.