A low power 1.2Gbps sync-less integrating PWM receiver

Abstract

A PWM receiver, without using a PLL or DLL, is proposed in this paper. This receiver does not need any synchronization (sync) bit sequence for locking on to the incoming data rate. No requirement of sync bits increases not only link throughput, but also reduces overall link power by allowing quick burst-sleep-burst transitions. A PWM bit symbol is decoded by time-to-voltage conversions of PWM major and minor durations followed by a comparison between them. Three such decoders are used in a time interleaved fashion to extract three consecutive PWM bits to achieve 1.2Gbps bit rate. Jitter tolerance measurement shows a high frequency jitter tolerance of 0.45UI at 1.2Gbps. This PWM receiver is fabricated in 40nm bulk CMOS process. It consumes 5.5mW and occupies an area of 0.0389mm2.