Simulated and experimental effects of ESD on CMOS timing circuits

Abstract

The effects of an electrostatic discharge (ESD) event on a CMOS timing circuit were investigated experimentally and using computer simulations. Results are provided for cases when an ESD pulse was imposed on the original timing circuit, as well as when various protection schemes were incorporated in the circuit. Voltage spikes and timing errors were observed in the original timing circuit in both computer simulations and laboratory experiments. The beneficial effects of using ESD suppression devices were also observed in both cases. Similarities and differences between results obtained from computer simulations and laboratory experiments are discussed.