Advanced CMOS VLSI Technology for Low Power Analog System Design with High Gain

Abstract

This research article provides an insight about the important challenges involved in the low power analog system design using advanced CMOS VLSI approach. Reduction in the dimension of MOS base channel and reduction in gate oxide results in greater advancement in terms of area of the chip, operating speed, and reduction of power consumption (mainly in digital components). In other words, few disadvantage also exists in term of leakage of power, operating characteristics, and life of the IC. Also, advancement in scaled approach or technology reduces the supply voltage and it results in CMOS based VLSI analog system manufacturers to face new challenging solution to ensure required operating characteristics.