LiB: a cell layout generator

Abstract

An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB.<>