A new back-gate SOI high voltage device with a compound layer

Xiaoming Yang, Bo Zhang, X. Luo, Tianqian Li
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引用次数: 3

Abstract

A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side, and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance. The breakdown voltage and electric field profile are researched for the new structure by using 2D MEDICI software. Simulation result shows that BG CL SOI-LDMOS can reach 557 V, 165.8 % higher than conventional SOI, at 1μm-thick buried oxide layer, 40 μm-length drift region and 240V back-gate voltage.
一种新型带复合层的反向SOI高压器件
为了提高绝缘子上硅(SOI)器件的击穿电压,提出了一种采用复合层(BG CL SOI- ldmos)的后栅SOI高压器件。引入复合层可以有效抑制源侧表面电场增益,增加埋地氧化层电场。在比导通电阻不变的情况下,器件击穿电压显著提高。利用二维MEDICI软件研究了新结构的击穿电压和电场分布。仿真结果表明,在埋置氧化层厚度为1μm、漂移区长度为40 μm、后门电压为240V时,BG CL SOI- ldmos的电压可达557 V,比传统SOI高165.8%。
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