A Versatile Test Set Generation Tool for Structural Analog Circuit Testing

Abstract

This work presents a low cost automatic test generation tool for structural analog testing. With the spice netlist and technology models of the circuit to be tested, a fault list (of size F) is generated, considering a defect modeling provided by the user. The tool interacts with a spice simulator, simulating the fault-free and F faulty circuits. The test limits used to calculate the fault coverage may be either defined by the user or automatically computed considering the process variability of the fault-free circuit. The test development considers DC, AC (single tone) and transient (step) stimuli applied at the primary circuit inputs, computing the obtained fault coverage when taking different circuit nodes as observation points. The final test set determination relies on a fault dictionary that helps maximizing the fault coverage, at the same time as minimizing the test application time and exposing undetected faults. A case study, consisting in a second order Butterworth filter, built with a 180 nm fully-differential OpAmp is presented, considering a resistive defect modeling to generate the fault list. For this case study, the tool indicates a fault coverage of 96.25% considering four tests (two AC and two DC).