A vertical power device conductive assembly at wafer level using direct bonding technology

Abstract

The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding electrical and thermal behavior. In addition, the characteristics of the power device can be optimized independently from mechanical requirements on Silicon thicknesses. The technological integration is described and analyzed. The paper focuses afterwards on the electrical characterizations of these new components. The interest of this partial packaging technique is related to the ease of implementation of numerous power devices used for example in interleaved converter topologies where up to ten to fourteen inverter arms can be connected in parallel to significantly reduce the needed filtering elements.