An iterative hardware Gaussian noise generator

Abstract

The quality of generated Gaussian noise samples plays a crucial role when evaluating the bit error rate performance of communication systems. This paper presents a new approach for the field-programmable gate array (FPGA) realization of a high-quality Gaussian noise generator (GNG). The datapath of the GNG can be configured differently based on the required accuracy of the Gaussian probability density function (PDF). Since the GNG is often most conveniently implemented on the same FPGA as the design under evaluation, the area efficiency of the proposed GNG is important. For a particular configuration, the proposed design utilizes only 3% of the configurable slices and two on-chip block memories of a Virtex XC2V4000-6 FPGA to generate Gaussian samples within up to /spl plusmn/6.55/spl delta/, where /spl delta/ is the standard deviation, and can operate at up to 132 MHz.