IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off

Abstract

With increasing complexity and focused efforts to achieve feature and functionality loaded digital design, there has been developing a keen interest to invest time on scope and quality of verification since a decade or more. From functional to static evaluation checks, from driving architecturally defined inputs to fuzzy logic through ports, from black-boxed DUT to white-boxed assertion analysis – what not! The dynamics of functional validation have increased to a great extent. The more complex is the design, the more is its functional verification collateral connectivity. It is evident that there are iterative processes during the IP-SoC development cycle as these involve intense human efforts to code and verify the changes. The standard UVM components and objects – sequencer, driver, monitor, scoreboard, transaction item, instantiation and connection for BFMs, additionally, several cross-module references, sequences, checkers, assertions, testcases and regression management, functional coverage and exclusions etc. are required to be replicated for any change in the design configuration of a IP in SoC. The proposed methodology attempts to strategically reduce IP’s verification environment bring up time in the execution cycle and aims at reduced effort towards verification sign-off. It also proposes an ML (Machine Learning) plug-in to extract a standard template out of already available verification collaterals.