Architecture of the high-speed standard basis multiplier with delay-boxes over GF(2/sup m/)

Abstract

We design an alternative of the high-speed parallel multiplier based on the standard basis over GF(2/sup m/). it is composed of three types of general multiplier cells (GMC) and two types of delay boxes (DB) When we implement the proposed multiplier over GF(2/sup 8/) by using 0.8 /spl mu/m CMOS standard cell library, at the 185 MHz clock-rate, the implemented multiplier has less complexity, ie, a 25% reduction from that of Berlekamp (1982) and a 33% reduction from that of Jain et al., (1998). For power-consumption, the implemented multiplier has a 29% reduction from that of Jain.