Parallel Pipelined VLSI Architectures for Lifting-Based Two-Dimensional Forward Discrete Wavelet Transform

Abstract

In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed architectures is that they only require a total temporary line buffer (TLB) of size N and 3N in 5/3 and 9/7, respectively.