Illustration of the importance of on-chip self and mutual inductances

Abstract

Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. In this paper, we show the influence of on-chip self and mutual inductances on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and on the other with the drivers in opposite directions. The differences observed, when the currents in the lines flow in the same direction as opposed to the cases when the currents are in opposite directions shows clearly the influence of mutual inductance. A second comparison ignoring inductive effects shows a discrepancy rate reaching as high as 50% for the output switching delay.