Interleaved Edge Routing in Buffered 3D Mesh & CMesh NoC

Abstract

Many-core processors are widely used in areas such as cloud computing, big data processing, high performance computing and data centre applications. Network on Chip (NoC) is the preferred interconnect solution which can overcome scalability issues and communication bottleneck associated with them. Minimal latency, area and better throughput are the key performance parameters of on-chip network design. The performance can be greatly enhanced by replacing 2D NoC communication infrastructure with 3D NoC where multiple NoC layers are integrated using high-speed Through Silicon Via (TSV) based vertical links. 3D router designs incur extra power and area in addition to integration issues such as reliability and fabrication problems, related with TSV based interconnection. In this paper, we utilize an asymmetrical routing technique in Mesh & CMesh topologies where we make interleaved connections between edge routers in 3D buffered on-chip network to improve NoC performance. Simulation results indicate that our design approach, MML (Modified Multi Layer) network, has significant improvement in throughput and latency reduction on comparing with conventional buffered networks which employ same number of routers.