NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA) Pub Date : 2020-02-01 DOI:10.1109/HPCA47549.2020.00048

Changmin Lee, Wonjae Shin, D. Kim, Yong-Ho Yu, Sung-Joon Kim, Taekyeong Ko, Deokho Seo, Jongmin Park, Kwanghee Lee, Seon-Jun Choi, Namhyung Kim, G. Vishak, A. George, V. Vishwas, Donghun Lee, Kang-Woo Choi, Chang-In Song, Dohan Kim, Insu Choi, I. Jung, Y. Song, Jinman Han

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引用次数: 8

Abstract

Currently, there are two representative non-volatile dual in-line memory module (NVDIMM) interfaces: a proprietary Intel DDR-T and the JEDEC NVDIMM-P, which are not supported by existing platforms. Adoption of new platform is costly and measuring its efficiency of migrating to the new platform is much more complex. This study is an alternative way of them—finding a new memory device that can be supported by all existing systems. In this paper, we propose an NVDIMM architecture with several system-wide mechanisms to allow the synchronous DDR4 memory interfaces to support non-deterministic (asynchronous) timing. The proposed memory architecture is implemented as a real device prototype, and also evaluated using synthetic and real workloads on an x86-64 server system.

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NVDIMM-C:兼容标准DDR内存接口的字节可寻址非易失性内存模块

目前，有两种具有代表性的NVDIMM (non-volatile dual in-line memory module)接口:Intel专有的DDR-T和JEDEC的NVDIMM- p，现有平台不支持这两种接口。采用新平台是昂贵的，并且衡量其迁移到新平台的效率要复杂得多。这项研究是他们的另一种方式——找到一种新的存储设备，可以被所有现有系统支持。在本文中，我们提出了一种具有多种系统级机制的NVDIMM架构，以允许同步DDR4内存接口支持非确定性(异步)定时。提出的内存架构作为一个真实的设备原型实现，并在x86-64服务器系统上使用合成和真实工作负载进行了评估。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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