A SRAM design based on tetrad and hierarchical dynamic decoding technology

Li Xuan
{"title":"A SRAM design based on tetrad and hierarchical dynamic decoding technology","authors":"Li Xuan","doi":"10.1109/ITAIC.2014.7065018","DOIUrl":null,"url":null,"abstract":"Static random access memory (SRAM) is a type of static access memory which employs latching circuitry to store data. It can save the data without refreshing logic circuit. In order to obtain a high speed and low power consumption SRAM, the layout of the memory array is critical. A new SRAM structure is analyzed and proposed in this paper. The proposed design uses tetrad technology and hierarchical dynamic decoding technology. The whole capacity of the proposed SRAM is 64*256 bits, and distributed in the four corners of the chip. Decoding circuit is symmetrical, and divided into the low 32-bit and high 32-bit. Compared to the traditional decoding circuit, it has faster speed, more compact structure, and smaller size.","PeriodicalId":111584,"journal":{"name":"2014 IEEE 7th Joint International Information Technology and Artificial Intelligence Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 7th Joint International Information Technology and Artificial Intelligence Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITAIC.2014.7065018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Static random access memory (SRAM) is a type of static access memory which employs latching circuitry to store data. It can save the data without refreshing logic circuit. In order to obtain a high speed and low power consumption SRAM, the layout of the memory array is critical. A new SRAM structure is analyzed and proposed in this paper. The proposed design uses tetrad technology and hierarchical dynamic decoding technology. The whole capacity of the proposed SRAM is 64*256 bits, and distributed in the four corners of the chip. Decoding circuit is symmetrical, and divided into the low 32-bit and high 32-bit. Compared to the traditional decoding circuit, it has faster speed, more compact structure, and smaller size.
基于四分体和分层动态解码技术的SRAM设计
静态随机存取存储器(SRAM)是一种采用锁存电路来存储数据的静态存取存储器。无需刷新逻辑电路即可保存数据。为了获得高速低功耗的SRAM,存储器阵列的布局是至关重要的。本文分析并提出了一种新的SRAM结构。本设计采用四分体技术和分层动态解码技术。该SRAM的总容量为64*256位,分布在芯片的四个角上。译码电路是对称的,分为低32位和高32位。与传统的译码电路相比,具有速度更快、结构更紧凑、体积更小等优点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信