{"title":"A SRAM design based on tetrad and hierarchical dynamic decoding technology","authors":"Li Xuan","doi":"10.1109/ITAIC.2014.7065018","DOIUrl":null,"url":null,"abstract":"Static random access memory (SRAM) is a type of static access memory which employs latching circuitry to store data. It can save the data without refreshing logic circuit. In order to obtain a high speed and low power consumption SRAM, the layout of the memory array is critical. A new SRAM structure is analyzed and proposed in this paper. The proposed design uses tetrad technology and hierarchical dynamic decoding technology. The whole capacity of the proposed SRAM is 64*256 bits, and distributed in the four corners of the chip. Decoding circuit is symmetrical, and divided into the low 32-bit and high 32-bit. Compared to the traditional decoding circuit, it has faster speed, more compact structure, and smaller size.","PeriodicalId":111584,"journal":{"name":"2014 IEEE 7th Joint International Information Technology and Artificial Intelligence Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 7th Joint International Information Technology and Artificial Intelligence Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITAIC.2014.7065018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Static random access memory (SRAM) is a type of static access memory which employs latching circuitry to store data. It can save the data without refreshing logic circuit. In order to obtain a high speed and low power consumption SRAM, the layout of the memory array is critical. A new SRAM structure is analyzed and proposed in this paper. The proposed design uses tetrad technology and hierarchical dynamic decoding technology. The whole capacity of the proposed SRAM is 64*256 bits, and distributed in the four corners of the chip. Decoding circuit is symmetrical, and divided into the low 32-bit and high 32-bit. Compared to the traditional decoding circuit, it has faster speed, more compact structure, and smaller size.