A Mixed Analog-digital Chip For A Phased-array Signal Processor

Abstract

PHASED-ARRAY TECHNIQUES are used in signal processing applications in radar, sonar, geophysics, and nondestructive testing. An image is generated by amplifying, rephasing, optionally time delaying, and summing the signals from the array. Figure 1 dustrates the process of electronically forming an image by properly taking into account the arrival time differences across the array of waves from a point source. The signal-processing corrects for these arrival-time differences by properly time delaying the signals prior t o summation. Sections of the processor have been implemented in a mixed analoy/digital VLSI circuit as illustrated in Figure 2. The monolithic circuit is used t o digitize two channels of analog signals, compress or decompress the data, and impose the necessary time delays for coherent summation. Following digitization of the signals, the 8 b output from the A/D is delayed in a FIFO which has lOOns resolution, designated as the fine time delay in Figures 2 and 3. This provides the time delay difference between adjacent channels with the delay being updated during beam formation t o achieve dynamic focusing (focal length change with increasing distance). The FIFO is a first-in, first-out buffer which is used to store and output data sequentially from a three-transistor cell, with a controllable time delay between the input and output. An effective 50ns time delay quantization per channel is achieved by rephasing the A/D triggers at appropriate times in the beam formation, and properly adjusting the lengths of the fine time delays. The output signals from these fine time delay circuits form the addresses for a 128x12 SRAM which stores a 12b look-up table. T h s remap table allows the signal amplitude t o be compressed or decompressed, depending upon the signal processing application. The table is written into the SRAM by the system during nonimaging times at a l0MHz rate. The SRAM is designed to be read at 20MHz for timesharing between the two channels, each with lOMHz throughout, to save chip area.