Design of digit serial FIR filter using shift add architecture

Abstract

Most of the researchers have developed the solution for designing multiplier and accumulator (MAC) section used in Digital signal processor by using number of algorithms and architectures. Multiple constant multiplications (MCM) is a factor which dominates the complexity of many digital signal processing systems. This paper deals with the designing of digit serial FIR filter which will reduce the complexity of multiple constant multiplications in digital signal processors by reducing the gate area and power consumption. In order to achieve this, shift/ add architecture concept is proposed.