Functional Fmax test-time reduction using novel DFTs for circuit initialization

Ujjwal Guin, T. Chakraborty, M. Tehranipoor
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引用次数: 4

Abstract

Using functional test for Fmax analysis is still the only effective method used in practice in spite of the fact that the test cost associated with functional Fmax test remains to be a major problem. In this paper, we develop novel design-for-testability (DFT) structures to considerably reduce the cost of initializing the circuit during functional test. The proposed architectures take advantage of existing DFT structures to reduce the overall cost of hardware and have no impact on the circuit timing. Our implementations of these DFT structures for initializing ITC'99 benchmark circuit b19 demonstrate the effectiveness of these techniques in reducing test time and thus the overall test cost.
利用新颖dft减少电路初始化的功能Fmax测试时间
使用功能测试进行Fmax分析仍然是实践中使用的唯一有效的方法,尽管与功能Fmax测试相关的测试成本仍然是一个主要问题。在本文中,我们开发了新的可测试性设计(DFT)结构,以显着降低在功能测试期间初始化电路的成本。所提出的体系结构利用现有的DFT结构来降低硬件的总体成本,并且对电路时序没有影响。我们对初始化ITC'99基准电路b19的这些DFT结构的实现证明了这些技术在减少测试时间和总体测试成本方面的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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