Multi-Bit Error Correction Coding with Crosstalk Avoidance Using Parity Sharing Technique for NoC

Abstract

In the presence of crosstalk, reliable on chip communication in deep-submicron technology is becoming a major challenge. NoC (Network on Chip) interconnects in noisy environment are highly prone to random errors and burst errors. Hence, Error Correction Code (ECC) combined with noise tolerance technique is required to make the NoC communication reliable. A Multi-bit Error Correction Coding with crosstalk avoidance using Parity Sharing technique (MECCPS), which corrects (3N/4) random error bits or (3N/4) bits of burst error for a N bit input data is proposed where N=2^M for M>1. Reliability in terms of probability of residual error of the coding technique, link swing voltage of the interconnects and power consumption of the NoC interconnect are calculated to determine the performance of the MECCPS technique. The MECCPS technique has 17% less area than that of Joint Crosstalk Aware Multiple Error Correction (JMEC), but slightly higher area than those of Duplicated Two-Dimensional Parities (DTDP). The probability of residual error, link swing voltage and power consumption of link of MECCPS technique are lower than that of above mentioned techniques due to higher error correction capability. There is an overhead in power and delay for the MECCPS codec when compared to above mentioned codec which can be compensated for higher error bits correction capability.