High-Throughput Hardware Implementation for Haraka in SPHINCS+

Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang
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引用次数: 2

Abstract

SPHINCS+, a hash-based signature scheme, has stood out as one of the four winners in the post-quantum cryptography (PQC) competition hosted by the U.S. National Institute of Standards and Technology (NIST). However, the slow signing speed forms a bottleneck for applications. Therefore, a kind of short-input hash function named Haraka is recommended as the third instantiation in SPHINCS+ due to its advantage in processing speed. In this work, we propose four hardware architecture schemes for Haraka in SPHINCS+, denoted as Case I to Case IV. Several optimization methods are combined and applied in different cases to perform the trade-off between area and throughput for different application scenarios. We code our designs in System Verilog language and synthesize them under the TSMC 28-nm CMOS technology. The experiment results show that Case IV achieves the best throughput and the most efficient performance, about 81.92 Gbps and 1.26 Mbps/GE, respectively, which also significantly outperforms the state-of-the-art implementation of Haraka and the advanced hardware implementation of the SHA-3 hash function.
Haraka在SPHINCS+中的高吞吐量硬件实现
在由美国国家标准与技术研究院(NIST)主办的后量子密码学(PQC)竞赛中,基于哈希的签名方案SPHINCS+脱颖而出,成为四个获胜者之一。但是,缓慢的签名速度会成为应用程序的瓶颈。因此,由于在处理速度上的优势,推荐使用一种名为Haraka的短输入哈希函数作为SPHINCS+中的第三个实例化。在这项工作中,我们为SPHINCS+中的Haraka提出了四种硬件架构方案,分别为Case I到Case IV。在不同的情况下,我们结合了几种优化方法,以在不同的应用场景下实现面积和吞吐量之间的权衡。我们用System Verilog语言进行编码,并在台积电28纳米CMOS技术下进行合成。实验结果表明,Case IV实现了最好的吞吐量和最有效的性能,分别约为81.92 Gbps和1.26 Mbps/GE,这也显著优于Haraka的最先进实现和SHA-3哈希函数的先进硬件实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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