High Performance Architecture of a Graphics Accelerator

Abstract

The Bresenham's line algorithm is one used to draw a straight line determined by two points, which is often implemented in graphics chips. In order to speed up the drawing performance, the hardware circuit in this paper is designed by an FPGA based on its advantages of synchronous execution and multiplexing of multiple circuits. This FPGA hardware circuit is verified with a three-axis motion controller platform which is composed of three two-phase stepping motors and three rotary screws. The Bresenham's line algorithm, to calculate the coordinates of the motion path of circles by using five groups of coordinate-operation units, is implemented in this work. The coordinates calculated by VerilogHDL and the coordinates of the motion path calculated by C language are compared to verify the correctness, and then the graph is drawn to present the results. The experimental results show that, by using one group of coordinate operation units as in the tradition and by using five groups of coordinate-operation units in this paper, their execution cycles turn out to be 21 and 6, respectively. Obviously, this work can achieve to accelerate the function of drawing.