Area-Efficient Processor for Public-Key Cryptography in Wireless Sensor Networks

Abstract

This paper presents a versatile public-key cryptographic processor suitable for wireless sensor networks which uses minimal hardware resources while maintaining high flexibility. The processor architecture is scalable and all hardware configurations support arbitrary bit-lengths and domain parameters. The tradeoffs between hardware area and timing for the public-key operations are demonstrated on the FPGA layer of the 25 mm Tyndall mote.