Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression

Ibrahim Haddadi, Issa Qiqieh, R. Shafik, F. Xia, M. A. N. Al-hayanni, Alexandre Yakovlev
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引用次数: 1

Abstract

Designing energy-efficient hardware continues to be challenging due to arithmetic complexities. The problem is further exacerbated in systems powered by energy harvesters as variable power levels can limit their computation capabilities. In this work, we propose a run-time configurable adaptive approximation method for multiplication that is capable of managing the energy and performance tradeoffs — ideally suited in these systems. Central to our approach is a Significance-Driven Logic Compression (SDLC) multiplier architecture that can dynamically adjust the level of approximation depending on the run-time power/accuracy constraints. The architecture can be configured to operate in the exact mode (no approximation) or in progressively higher approximation modes (i.e. 2 to 4-bit SDLC). Our method is implemented in both ASIC and FPGA. The implementation results indicate that our design has only a 2.3% silicon overhead, on top of what is required by a traditional exact multiplier. We evaluate the efficiency of the proposed design through a number of case studies. We show that our method achieves similar image fidelity as in the existing approximate methods, without a delay penalty. Further, the inclusion of the dynamic approximation techniques is justified by up to 62.6% energy savings when processing an image with a multiplier using 4-bit SDLC and 35% energy savings when using 2-bit SDLC. In addition, case study results show that the proposed approach incurs negligible loss in output quality with the worst PSNR of 30dB when using the 4-bit SDLC multiplier.
使用显著性驱动逻辑压缩的运行时可配置近似乘法器
由于算法的复杂性,设计节能硬件仍然具有挑战性。在由能量采集器供电的系统中,由于可变功率水平会限制其计算能力,因此问题进一步加剧。在这项工作中,我们提出了一种运行时可配置的自适应近似乘法方法,该方法能够管理能量和性能权衡,非常适合这些系统。我们方法的核心是一个意义驱动逻辑压缩(SDLC)乘法器架构,它可以根据运行时功率/精度约束动态调整近似值的水平。该架构可以配置为在精确模式(无近似值)或逐步更高的近似值模式(即2至4位SDLC)下运行。我们的方法在ASIC和FPGA上都实现了。实现结果表明,在传统精确乘法器所需的基础上,我们的设计只有2.3%的硅开销。我们通过一些案例研究来评估所提出的设计的效率。结果表明,该方法与现有的近似方法具有相似的图像保真度,且没有延迟损失。此外,当使用4位SDLC处理带有乘法器的图像时,包含动态近似技术可以节省高达62.6%的能量,而当使用2位SDLC处理图像时可以节省35%的能量。此外,案例研究结果表明,当使用4位SDLC乘法器时,该方法的输出质量损失可以忽略不计,PSNR最差为30dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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