Throughput-based network-on-chip topology generation and analysis

Abstract

This paper presents a new approach to meeting communication requirements of on-chip network systems. The method is based on the transaction-oriented protocol employed by on-chip components, and the fact that latency becomes the performance-impacting factor instead of bandwidth. A network-on-chip topology generation and analysis tool is presented which has the primary aim of generating on-chip topologies that will meet a given information throughput. The proposed methodology also incorporates contention estimation into the design phase, thus reducing execution time considerably by eliminating the need for multiple generation iterations. SystemC simulation results for two multimedia applications with differing throughput requirements are presented, and the method provides comparable performance to regular topologies while using, on average, half the resources.