{"title":"Design of Improved Content Addressable Memory Using QCA Technology","authors":"Sujatha Kotte, Ganapavarapu Kanaka Durga","doi":"10.1109/ESDC56251.2023.10149853","DOIUrl":null,"url":null,"abstract":"Data stored at various memory locations of the memory can be accessed by using different searching algorithms. Conventionally, random access memory (RAM) the address-based memory detection method has been used in many computational systems. A new content addressable memory (CAM) cell is proposed in this paper. The proposed memory cell is designed using the QCA technology the three-input majority gate and five-input minority gates are used in the design. QCA designer tool is used for the simulations and its functionality is also verified using this tool. Additionally, performance comparison of proposed CAM cell is performed by considering the parameters like power, area and clock latency. It has been observed that the proposed CAM cell is more robust and less sensitive to temperature variations compare to existing structures.","PeriodicalId":354855,"journal":{"name":"2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESDC56251.2023.10149853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Data stored at various memory locations of the memory can be accessed by using different searching algorithms. Conventionally, random access memory (RAM) the address-based memory detection method has been used in many computational systems. A new content addressable memory (CAM) cell is proposed in this paper. The proposed memory cell is designed using the QCA technology the three-input majority gate and five-input minority gates are used in the design. QCA designer tool is used for the simulations and its functionality is also verified using this tool. Additionally, performance comparison of proposed CAM cell is performed by considering the parameters like power, area and clock latency. It has been observed that the proposed CAM cell is more robust and less sensitive to temperature variations compare to existing structures.