Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization

Abstract

As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI physical design. To the best of the authors' knowledge, this paper develops the first physical design technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.