Hot-carrier reliability of bipolar transistors

Abstract

A study of bipolar degradation over a range of stress and measurement conditions is presented. It is shown that the excess base current, Delta I/sub B/, varies in a power-law manner with J/sub C/, I/sub R/, and t. The I/sub R/ dependence results from a significant nonlocal effect in electron temperature that occurs at the periphery of the emitter due to the narrow depletion width. A quasistatic model of the degradation, suitable for SPICE circuit simulation, is presented and used to simulate the degradation of a BiCMOS inverter and differential pair circuit. The simulation of an advanced BiCMOS process indicates a degradation in the low-to-high propagation delay of 7% and 300 K and 3% at 110 K after 10 years of operation with C/sub L/=2 pf and V/sub CC/=5.5 V. For emitter-coupled pair circuits, the base current degradation can create a voltage drop across the base resistance, resulting in an additional offset voltage component. With the modeling methodology presented, one can predict the effect of varying the emitter-extrinsic-base junction doping profile on circuit reliability.<>