Fast carry free adder design using QSD number system

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993 Pub Date : 1993-05-24 DOI:10.1109/NAECON.1993.290791

A. Awwal, J. U. Ahmed

引用次数: 15

Abstract

A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<>

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采用QSD数字系统的快速免进位加法器设计

设计了一种高速并行全加法器，可以对两个修改过的有符号四进制数进行无进位加法。对于数字实现，符号位四进制数使用3位补码表示法表示。给出了加法器真值表及可能的电子和光学实现方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993

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