A CMOS Two-Stage Amplifier Design Methodology for CAD Tools

Abstract

This paper presents an automated design methodology for a CMOS two-stage operational amplifier as a basic analog building block. The proposed methodology relies on a set of complex-less mathematical equations based on a current-based MOSFET model, which describes all operating regions of the MOSFET. As a result, this design methodology offers an efficient, reliable, and fast method for transistor’s sizing in high-performance analog integrated circuits without the need for the deep knowledge of an experienced analog-circuit designer. Moreover, a key feature of the proposed methodology is a trade-off between normalized total Current Excess Factor (CEF) and Area Excess Factor (AEF) of the circuit topology to achieve high power and area efficiency.